This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
In modern circuit design, memory and related mechanisms support dual voltage rails for bitcell core (VDDCE) and periphery circuitry (VDDPE). VDDCE lowering is limited by bitcell retention voltage and is held at higher voltages compared to VDDPE. However, VDDPE lowering is usually limited by internal circuitry. Typically, VDDPE may potentially limit power savings on chip. Large range level shifting may require level shift of all inputs inside memory from low VDDPE to higher VDDCE domain, which may enable VDDPE to be lower than VDDCE. However, a disadvantage is that this implementation may cause delay penalty to all signals going through level shifters inside memory, which may lead to timing degradation, such as memory access time and input pins setup time.
Using level-shifters can introduce extra delay for input and output signals that increases input setup time and access time of memory. Further, level shifter topology can be prone to DC path issues during initial power-up and in case of floating inputs. Since the inputs are in another power domain, some operation modes allow them to be floating while the level shifter is powered-up, which results in a DC path passing through the level shifter. Sometimes, during initial power-up, the level shifter can resolve to a differential state slowly, and the level shifter may not be able to sustain a strong low voltage level on the output, since a pull-down path of the level shifter can be controlled by the other power domain. This results in a DC path for next stage gates, as well as power-up failures.